The present invention relates to string digital-to-analog converters (DACs), in particular, to charge boosting in string DACs.
String DACs convert a digital word into a corresponding analog signal. Generally, string DACs of single string type include a series connected resistor string and are used for low to moderate resolution. Dual-string DACs have been made with the impedance of the second string unit resistor significantly higher than the impedance of the first string unit resistor to reduce the loading effect to an acceptable level. Dual stage DACs also have used voltage buffers to buffer an intermediate output voltage from the first stage DAC to the second stage DAC, which also may employ a string DAC architecture.
Dual-string DACs typically include two series connected resistor strings and two switch networks respectively for each resistor string. The output of the first resistor string, which is typically used for converting the most significant bits (MSBs) of the digital word, is coupled to the input of the second resistor string, which is used for converting the least significant bits (LSBs) of the digital word.
In dual-string DACs, code transitions in MSB DAC conversion can lead to “glitches” in the LSB DAC conversion due to voltage mismatch. For example, voltage-mode DAC major code transition glitch energy, typically measured in Vsecs, and glitch magnitude, typically measured in Volts peak to peak or V(pk-pk), are transient properties indicative of non-ideal transient responses in the DAC. Glitches can be broadly classified as two types—fast glitches and slow glitches.
Fast glitches occur at the major code transition (MCT) in dual string DACs as a result of high speed charge re-distribution when the LSB DAC is re-coupled to the MSB DAC in the new circuit configuration. This is normally dominated by the high speed [dis-]charging of the LSB DAC reference terminal and the associated switching network as per example shown in FIG. 1(a), which illustrates a MCT glitch causing a fast current path in a simplified dual-string DAC. Fast glitches are generally due to high speed switching and charge re-distribution in low impedance paths, for example between devices that are coupled via metal interconnections, such as switching networks.
Slow glitches, on the other hand, are generally dominated in mult-string DACs by distributed RC settling of the LSB DAC circuitry. FIG. 1(b) illustrates a MCT glitch causing a slow current path in a simplified dual-string DAC. The glitching caused by code transitions also limits the settling time of multi-string DACs as the self-capacitance of the DAC network takes significant time to be charged via the MSB DAC network. The impedance element, such as resistance, has an intrinsic bandwidth due to parasitic capacitance, which limits the settling speed.
In such architecture where output changes are required, the output capacitance is charged via the DAC. The impedance (resistance) of this network limits the charging current and thus the settling speed. This impedance is also important to the DAC static power consumption. It is desirable to have lower power consumption, which is conventionally achieved via higher DAC string impedance, and also reduced settling time, which is conventionally achieved via lower DAC string impedance. Thus, there is a need in the art to overcome this power-speed tradeoff limitation.
Therefore, the inventor recognized a need in the art for increased speed in DACs without substantial additional DAC static power consumption.